Closing the Loop: Resource-aware Hybrid NAS Guided by Analytical and Hardware-Calibrated Quantum Cost Modeling

Abstract

Hybrid quantum-classical neural networks (HQNNs) integrate quantum circuits with classical layers, each operating under fundamentally different computational paradigms, which makes hardware resource estimation challenging. The training of quantum circuits on real devices requires thousands of circuit executions, which is impractical on current NISQ devices. Therefore, most HQNNs are evaluated on classical simulators, with hardware cost approximated using floating-point operations (FLOPs). However, FLOPs and existing quantum resource estimation methods (e.g., gate counts) overlook key quantum hardware-specific factors such as gate durations, limited qubit connectivity, and noise, all of which ultimately determine the true cost and scalability of quantum circuits. In this paper, we propose an analytical quantum cost model that estimates quantum hardware resources using real backend calibration data, incorporating gate durations, routing overheads, and noise-induced sampling inefficiencies. To complement this, we develop a classical cost model that converts FLOPs into device-specific throughput, enabling a unified time-based representation of hardware resource cost for both subsystems of HQNNs. Building on these analytical models, we present Hyb-HANAS, a hardware-aware hybrid neural architecture search framework, which jointly optimizes accuracy, hardware cost, and parameter count using NSGA-II. Hyb-HANAS identifies Pareto-optimal trade-offs and cross-domain co-adaptation between classical and quantum components of HQNNs. Beyond NAS, the proposed analytical quantum cost model is broadly applicable to quantum hardware benchmarking, compiler evaluation, and training-time estimation of quantum circuits on NISQ devices.