Moveless: Minimizing QEC Qverhead on QCCDS via Versatile Execution and Low Excess Shuttling

Abstract

One of the most promising paths towards large scale fault tolerant quantum computation is the use of quantum error correcting codes. The majority of popular codes are stabilizer codes, in which error information is extracted via the repeated execution of a set of commuting stabilizer measurement circuits and then decoded. Just like every other quantum circuit, these circuits must be compiled to hardware in a way to minimize the total physical error introduced into the system, for example either due to high latency execution or excessive gates to meet connectivity limitations of the target hardware. However, unlike arbitrary quantum circuits, all syndrome extraction circuits have several common properties, for example they have a bipartite connectivity graph, consist only of commuting subcircuits, and have a set of ancilla which are indistinguishable between measurement rounds, among others. For the most part, compilation methods have aimed at being generic, able to map any input circuit into executables on the hardware, and therefore cannot appropriately exploit these properties and result in executables which have higher physical error. In the case of modular trapped ion systems, specifically QCCDs, this corresponds to the insertion of excessive shuttling operations necessary to realize arbitrary qubit interactions. We propose a compilation scheme explicitly tailored for the structural regularity of quantum error correction code physical circuits, with the primary objective of minimizing circuit latency from shuttling operations. Our compiler's success is predicated on several key observations: 1. only ancilla or data (but not both) should be shuttled, 2. stabilizers can be executed in any order meaning we can dynamically modify circuit execution on a per-cycle basis 3. ancilla are indistinguishable meaning any can be selected to begin a stabilizer measurement and since only ancilla are shuttled, we retain a fixed-point mapping between cycles, and 4. QCCD hardware limits the number of parallel operations equal to the number traps in the system bounding the rate of stabilizer measurement meaning fewer ancilla are necessary and can be easily reused. Our resulting compiler, leads to QEC circuits which are on average $3.38 \times$ faster to execute (by up to $5.24 \times$) and therefore incur lower physical error. For codes with good decoders, e.g. the color code and surface code, these improvements lead to up to two orders of magnitude of improvement in logical error rates with realistic physical error rates.