Circuit simulation of readout process toward large-scale superconducting quantum circuits
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Abstract
The rapid scaling of superconducting quantum computers has highlighted the impact of device-level variability on overall circuit fidelity. In particular, fabrication-induced fluctuations in device parameters such as capacitance and Josephson critical current pose significant challenges to large-scale integration. We propose a simulation methodology for estimating qubit fidelity based on classical circuit simulation, using a conventional Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This approach enables the evaluation of the performance of superconducting quantum circuits with 10000 qubits on standard laptop computers. The proposed method provides an accessible tool for the early stage assessment of large-scale superconducting quantum circuit performance.