Delay Balancing With Clock-Follow-Data: Optimizing Area Delay Tradeoffs for Robust Rapid Single Flux Quantum Circuits
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Abstract
This article proposes an algorithm for synthesis of clock-follow-data designs that provide robustness against timing violations for rapid single-flux quantum (RSFQ) circuits, minimizing area costs subject to a given performance constraint. Since all RSFQ logic gates must be clocked, properly sequencing the data flow is a challenging problem that often requires the insertion of many path balancing D flip-flops (DFFs), leading to a substantial increase in area. To address this challenge, we present an approach to insert DFFs and schedule their clock arrival times, partially balancing the delays within the circuit. Our algorithm achieves a target throughput while minimizing area overhead. Our algorithm can account for expected timing variations and, by adjusting the bias of the clock network and clock frequency, the resulting circuits can adjust for unexpected timing violations postfabrication. Quantifying the benefits of our approach with a benchmark suite with nominal delays, we yield an average 1.48x improvement in area delay product (ADP) over high frequency full path balancing designs and a 2.07x improvement in ADP over the state-of-the-art (SOTA) robust circuits provided by SOTA multiphase clocking solutions.