Near-Minimal Gate Set Tomography Experiment Designs

Abstract

Gate set tomography (GST) is a technique for self-consistently and precisely estimating the entire gate set of a quantum processor. GST carries nontrivial experimental cost, and as such the use of GST in practice has so far been limited to characterizing subsets of systems of at most two qubits at anyone time. In this work we present a new protocol for streamlining GST experiment designs by stripping away nearly all of the redundancy present in a traditional GST experiment. We do so by determining how GST base circuits (called “germs”) are sensitive to variations in particular gate set parameters, and leverage this information to identify and subsequently strip out redundancy across a germ set as a whole. We present the application of this new protocol to GST experiment designs for two-qubit systems and show that we can reliably produce experiment designs approaching information theoretic lower bounds in size. We demonstrate in both simulation and in a theoretical analysis based on the Fisher information that these streamlined experiment designs nonetheless maintain the Heisenberg-like precision scaling properties of traditional GST. Moreover, we show that in practice it is possible using this technique to achieve a final precision in our estimates comparable to those of much larger experiment designs using many times fewer circuits overall. We also discuss the impacts of this technique for the prospects of scaling up the practical use of GST for three-qubit systems.