Majorization-based benchmark of the complexity of quantum processors

Abstract

Here, we propose the use of the majorization-based indicator for quantum computation complexity introduced in Vallejos et al. (Phys. Rev. A 104:012602, 2021) as a tool to benchmark the complexity within reach of quantum processors, when taking into account hardware and noise constraints. By considering specific qubit systems and native gate sets of currently available technologies, we numerically simulate the operation of various quantum processors in the presence of typical types of noise. We characterize their complexity for different native gate sets, qubit connectivity, and increasing number of gates. We identify and assess quantum complexity by comparing the performance of each device against benchmark lines provided by randomized Clifford circuits and Haar-random pure states. In this way, we are able to specify, for each specific processor, the number of native quantum gates which are necessary, on average, for achieving those levels of complexity. Moving toward real implementations, our results validate the use of the majorization-based indicator in the presence of noise. We determine how much noise one quantum processor can admit while maintaining high levels of complexity. Our benchmarking procedure can thus be used to set target levels for noise in quantum processors, while taking into account their physical constraints.