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Simulating Hamiltonian dynamics in a programmable photonic quantum processor using linear combinations of unitary operations

Yue Yu, Y. Chi, C. Zhai, Jieshan Huang, Q. Gong, Jianwei Wang·November 12, 2022
Physics

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Abstract

Simulating the dynamic evolutions of physical and molecular systems in a quantum computer is of fundamental interest in many applications 1,2 . Its implementation requires efficient quantum simulation algorithms 3–12 . The Lie-Trotter-Suzuki approximation algorithm, also well known as the Trotterization, is a basic algorithm in quantum dynamic simulation 3–5 . A multi-product algorithm that is a linear combination of multiple Trotterizations has been proposed to improve the approximation accuracy 13 . Implementing such multi-product Trotterization in quantum computers however remains experimentally challenging and its success probability is limited. Here, we modify the multi-product Trotterization and combine it with the oblivious amplitude amplification to simulta-neously reach a high simulation precision and high success probability. We experimentally implement the modified multi-product algorithm in an integrated-photonics programmable quantum simulator in silicon, which allows the initialization, manipulation and measurement of four-qubit states and a sequence of linearly combined controlled-unitary gates, to emulate the dynamics of a coupled electron and nuclear spins system. Theoretical and experimental results are in good agreement, and they both show the modified multi-product algorithm can simulate Hamiltonian dynamics with precision than conventional Trotterizations and a nearly deterministic success probability. certificate the multi-product algorithm in a quantum simulator based on linear combinations of operations, and promises the practical implementations of quantum dynamics simulations. Device fabrication. The integrated photonic four-qubit quantum simulator used to implement the linear combinations of unitaries for Hamiltonian simulation is designed and fabricated on the silicon nanophotonics platform. The devices are fabricated by the standard CMOS (complementary metal oxide semiconductor) process. First, spin a layer of photoresist on an 8-inch SOI (silicon on insulator) wafer with 220 nm thick top silicon and 3 µ m thick buried oxide. 248 nm deep ultraviolet (DUV) lithography is used to define the pattern of the silicon layer on the photoresist where single-mode waveguides are designed with a width of 500nm (widened to 4 microns in some areas to reduce transmission losses). The pattern is transferred from the photoresist layer to the silicon layer by double inductively coupled plasma (ICP) etching process to form waveguide and grating couplers. A deeply etched waveguide with an etching depth of 220 nm is used for the SFWM photon source, beam splitter(multimode interferometer) and phase shifter. A shallow etched waveguide with an etching depth of 70 nm is used for waveguide crossovers and grating couplers. A 1 µ m thick SiO 2 layer is deposited on the SOI wafer by plasma-enhanced chemical vapor deposition (PECVD) as an modified algorithm:

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